The present claimed invention relates to the field of semiconductor processing. More particularly, the present claimed invention relates to a novel low noise on-chip inductor with a shield comprising a grounded low resistive material and an electrically floating high resistive material.
Increasing demands for personal mobile communication equipment have motivated recent research activities to focus on the development of inexpensive, small size, low power consumption and low noise level systems. Silicon, with its mature technology, low fabrication cost as well as high packing density is recognized as the only material able to satisfy the needs of this rapidly growing communication market. To fulfill all the above-mentioned requirements, one of the most important and indispensable circuit components is the on-chip silicon-based spiral inductor.
Advances in technology are making it possible to develop radio frequency (RF) circuits on a single silicon chip. In radio frequency operation, substrate induced noise inherent in the silicon technology is one of the main factors that limits achieving high performance low noise transceivers. Low Noise Amplifiers (LNA), being the first stage in the receiving path, are an important building block of a single-chip transceiver. The primary goal for the LNA is to minimize the noise figure of the receiver. However, in addition to RF noise from transistors, the thermal noise from the substrate resistance contributes significantly to the overall noise figure of the LNA. On-chip inductors, which are essential circuit components in building LNAs, VCOs etc., often generate significant amounts of such substrate noise that will degrade the overall circuit performance tremendously.
Several approaches that help reduce the effect of substrate thermal noise have been reported. However, all have significant problems. One conventional approach makes some improvements by introducing a ground shielded bonding pad structure (see, e.g., A. Rofougaran, J. Y. C. Chang, M. Rofougaran and A. A. Abidi, xe2x80x9cA 1 GHz CMOS RF Front-End IC for a Direct Conversion Wireless Receiver, xe2x80x9cIEEE Journal of Solid State Circuits, vol.31, pp880-889, 1996). Unfortunately, a ground shield produces a large pad to ground capacitance.
Another conventional technique uses thick polyimide inter-level dielectric underneath on-chip inductors (see, e.g., Y. Nakahara, H. Yano, T. Hirayama, Y. Suzuki and A. Furakawa, xe2x80x9cImpact of interconnect Capacitance Reduction on RF-Si Device Performance, xe2x80x9cIEDM Tech. Dig., pp861-864, 1999). Though significant results may be achieved, tedious, non-conventional and expensive processing steps are required with this method.
Hence, the key challenges for building on-chip silicon-based inductors lie not only in achieving high quality factor but also in fabricating inductors having low noise performance. For silicon-based inductors, it has been reported that having Silicide ground shields underneath the inductor improves its noise performance (see, e.g., H. Fujii, H. Suzuki, H. Yoshida and T. Yamazaki, xe2x80x9cA0.15 xcexcm/0.6 dB-Nfmin RF BiCMOS Technology using Cobalt Silicide Ground Shields,xe2x80x9d IEEE BCTM, pp98-101, 2000).
FIG. 1A illustrates a schematic cross section of an on-chip silicon-based inductor 110 without a ground shield. Conventional semiconductor processing uses a very conductive silicon substrate 102. Without any ground shield, the thermal noise in the substrate 102 may be substantial. FIG. 1B shows a cross section of an inductor 110 and a plate type ground shield 120 made of CoSi2. FIG. 1C shows a ground shield patterned by trenches 130. Using a ground shield, however, leads to an unavoidable increase in the parasitic capacitance, which severely degrades the inductor""s 110 performance.
FIG. 2 shows figures of merit for the inductors 110 of FIGS. 1A-1C. FIG. 2 shows the quality factor as a function of frequency for each case. As FIG. 2 shows, the quality factor is lower with the trench ground shield 130 when compared to the unshielded inductor. The quality factor is still lower with the plate shield 120. Furthermore, FIG. 2 shows that shielding the inductor 110 degrades the resonant frequency.
Referring now to FIG. 3A and FIG. 3B, one conventional method adds a patterned electrically grounded low sheet resistance polysilicon shield 320 between the inductor 110 and the substrate 102. Studies have been conducted to investigate inductors 110 with such patterned low sheet resistance polysilicon ground shields 320. FIG. 3A also shows an underpass 111 connected to the inductor 110 by vias 115. The semiconductor also comprises an inter-metal dielectric layer 322 and a field oxide layer 324. Unfortunately, this technique may lead to an increase in the parasitic oxide capacitance (Cox). Effectively, this technique brings a new conductive silicon substrate (e.g., the polysilicon shield 320) which is electrically grounded and closer to the inductor 110 than the substrate 102. As seen, the substrate 102 has its own capacitance Csi and resistance Rsi. The capacitance Cs between the inductor 100 spiral and underpass 110 is also shown.
Additionally, this configuration results in degradation in the inductor""s performance. FIG. 4 shows a plot of the quality factor and inductance of an unshielded inductor with one shielded with low sheet resistance patterned polysilicon. As the graph shows, at 5 GHz there is considerable degradation of the quality factor. Additionally, above 4 GHz the inductance begins to rise significantly due to self resonance at high frequencies.
Thus, although low sheet resistance polysilicon or Silicide ground shields may improve the inductor""s noise performance, the quality factor and resonant frequency are degraded.
As yet another concern, in order to achieve widespread acceptance, and to ensure affordability, any method of forming an on-chip silicon-based inductor, which overcomes the above-listed drawbacks, should be compatible with existing semiconductor fabrication processes.
Thus, a need exists for a shielded on-chip silicon-based inductor having low noise characteristics. A further need exists for such an inductor that does not have a significantly degraded quality factor. A further need exists for an inductor and a method for forming the inductor wherein the inductor and the formation method meet the above needs and are compatible with existing semiconductor fabrication processes such that significant revamping of semiconductor capital equipment is not required.
The present invention provides a shielded on-chip silicon-based inductors having a low substrate thermal noise. The present invention provides for such an inductor that does not have a significantly degraded quality factor. The present invention provides for an inductor and a method for forming the inductor wherein the inductor and the formation method meet the above needs and are compatible with existing semiconductor fabrication processes such that significant revamping of semiconductor capital equipment is not required.
A novel complimentary shielded inductor on a semiconductor is disclosed. The inductor is fabricated in one or more layers of a semiconductor. A region of electrically floating high sheet resistance material is deposited between the inductor and the semiconductor substrate. The high resistive shield is patterned with a number of gaps, such that a current induced in the shield by the inductor does not have a closed loop path. The high resistive floating shield compliments a grounded low resistive shield to achieve higher performance inductors. In this fashion, noise in the substrate is reduced. The novel complimentary shield does not significantly degrade the figures of merit of the inductor, such as, quality factor and resonance frequency.
In one embodiment, both the high resistive shield and the low resistive shield are patterned to prevent formation of eddy current in the shield. In one embodiment, the grounded low resistive shield, which may be made of silicided polysilicon, is aligned to cover the gaps of the high resistive shield, such that the inductor may not xe2x80x98seexe2x80x99 the substrate.
In one embodiment, the grounded shield is made of patterned N-well (or P-well) structures. The N-well structures may be aligned such that they compensate for the gaps in the electrically floating high resistive shield.
In still another embodiment, the low resistive electrically grounded shield is made of patterned Silicide, which may be formed on portions of the substrate itself. The substrate projects into a portion of a field oxide layer between the rest of the substrate and the high resistive shield. Thus, the low resistive shield is formed to block the gaps in the high resistive shield.